This invention generally relates to lithography procedures for making semi-conductor devices; and more specifically, to aligning the layers of multiple layer semi-conductor devices.
Semiconductor devices are typically constructed with many layers of mask levels. Each of these mask level is typically aligned to the immediately previous level or to one of the previous levels. The relative position of these levels and the ability to control the levels determine how a particular level is designed and processed. The present state-of-the-art alignment methodology allows a current mask level to be aligned to only one of the previous levels. As devices become smaller, the ability to align several mask levels becomes important, and this present state-of-the-art one level-to-one level alignment methodology is not sufficient.
Alignment methodology is important, for example, in the case of contacts and MC, where one may wish to align to diffusions and to the gate at the same time. As a second example, alignment is important in situations, such as in the case of fabrication of a MINT DRAM cell, where one would need to align buried strip and Deep Trench and Isolation Trench. In another DRAM example, one may, wish to align Gate shallow trench and deep trench.
An object of this invention is to improve alignment methodologies for lithography.
Another object of the present invention is to provide an improved alignment methodology for lithography that allows one to optimize the alignment for the current level to two previous levels.
These and other objectives are attained, in a lithography procedure, with a method of aligning a third level to two previous levels, where the alignment mark location for the third level is calculated based upon the two previous levels in both the x- and y-directions.
A preferred embodiment of the invention relates to a lithography alignment method for aligning a third level of a semiconductor device relative to first and second previous levels of the device. The method comprises the steps of forming first and second patterns at the first and second levels respectively, and determining offsets of the first and second patterns in two orthoginal directions. An optimum location for a third pattern in the third level is then determined based on an average of the offsets of the first and second patterns.
This invention may use either an averaged position method for each level/chip or a weighted average position method, depending on the relative tolerances of each level/chip to improve significantly the alignment of the current level to previous levels. The present invention utilizes the principal that, if one knows the position of alignment marks for level A and for level B, one can then calculate the relative positions between levels A and B. Based upon this knowledge, one can then align the current level to a new alignment mark whose position/location is based on the relative positions of levels A and B. Thus, the third level is now aligned and placed at the optimum position. This methodology can be implement via software or a combination of software and a new set of alignment marks.
With the conventional prior art, one would optimize the alignment via an alignment tree and by choosing one level to align to. It has also been proposed previously that one aligns X-direction to one level and Y-direction to another level. This is an improvement over the conventional alignment methodology but it improves only one direction per level. The present invention allows one to optimize the alignment to two previous levels.
Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention.